61 St Matthew’s Gardens
CB1 2PH
Tel : +44 779060 2705
E-Mail :
PROFILE
Senior Physical Design engineer, I have 7
years experience in digital physical design.
Currently working for more than 3 years
in one of the most successful tech company in the
Now working on a 90nm project that I have
partly setup, I am in charge of the test strategy, implementation and support.
Diagnosing physical chip defects to analyze customer return as well as for
yield improvement has also become an important activity in my daily work.
WORK
EXPERIENCE
2004-now Digital Physical Designer, CSR
plc (
As described above, and in more details
further on.
2000-2004 IC physical implementer, Philips Semiconductor (Southampton)
Part of the
Technology Implementation Group, a team of 21 people, which produces back-end
work on storage devices and digital TVs, I was in charge of implementing blocks
from gate level netlist through to GDS2. Lots of
scripting and improvement projects was also performed
in order to increase the team efficiency and product time to market.
1999-2000 Process improvement analysis, ST Microelectronics (
Work placement in the R&D team, I
characterized normal and Bipolar Schottky diodes
1998 CMOS
IC fabrication AIME
(Toulouse – FRANCE)
As part of a university
program, from the mask to the in-package test simulations
1993-1994 System designer, Dream Electronique (
With the university collaboration, I
developed and implemented the hardware and software of an automatic fish
counter using a micro-controller HC11.
EXPERTISE
ü
RTL
edits for Test
ü
Basic
and physical RTL synthesis
ü
Memory
and BIST generation and integration
ü
Physical
memory defect analysis
ü
Block
level floorplanning, placement and power routing
ü
Test
synthesis (Adaptive Scan, On Chip Clocking, XOR Tree…)
ü
Test
pattern generation (Stuck-At, Transition, Bridging and IDDQ)
ü
Test
pattern simulation
ü
Power
strategy and analysis
ü
Timing,
Congestion and Power driven placement
ü
Clock
Tree generation and optimization (with clock gating insertion)
ü
Static
Timing Analysis (with multi-thread system)
ü
Synchronous
digital/analogue STA interface analysis (in Philips)
ü
Signal
Integrity (Voltage drop, Crosstalk, EM prevention and simulation)
ü
Formal
verification
ü
Physical
Verification
ü
ECO
and IPO including Verilog hand edits (in Philips)
ü
Physical
chip defect diagnosis
ü
Tester
program analysis and debug help (on Teradyne tester)
ü
Automation
and GUI scripting
TOOL
SKILLS
Within
CSR:
Synopsys
Design Compiler
(DC and DC topographical), DFT compiler, DFT Max, Physical Compiler (PC),
Jupiter XT, Astro, ICC, TetraMax,
Primetime (Pt), Pt DMSA, Pt SI, VCS, StarRCXT
Azuro
PowerCentric
Novas
Verdi
Verplex
Logical Equivalence Checker (LEC)
Calibre
Within Philips
Semiconductors and some in CSR:
Cadence
Design Planner, Silicon Ensemble,
Mentor Graphics
Calibre
Verplex
Logical
Equivalence Checker
(LEC)
Novas Debussy
N-schema, N-Trace , N-ECO
Software
TCL , TCL-TK , Perl , Unix, Microsoft software and FrameMaker.
ACHIEVEMENTS
Within CSR:
ü UWB/WiFi
digital block design on 90nm, about 600k instances with 70 memories
o
Project
setup, library preparation
o
Memory
generation (using a memory compiler) and connection
o
Initial
constraint generation
o
RTL
pipeclean and Physical Synthesis
o
Placement
prototyping
o
Test
Strategy studies to adopt the latest DFT features
o
Implementation
of a new test mode switching and a real clock at-speed testing
ü Chip diagnosis (standard cell
and memories)
o
Creation
of a TetraMax diagnosis TCL interface GUI
o
Creation
of a TCL memory bit mapping diagnosis script
o
Successfully
used my tools to debug important customer chip returns
ü 90nm Flow study and implementation
(using a taped out 130nm project)
o
Project
setup, library preparation
o
RTL
Physical Synthesis
o
Test
Strategy studies and implementation
o
Placement
prototyping and final
o
Test
pattern generation and simulation
o
Clock
Tree synthesis
o
Routing
with Xtalk avoidance
o
Parasitic
extraction with Multi-thread implementation
o
Static
Timing Analysis with DMSA implementation
ü BlueTooth digital block design on a
130nm
o
RTL
synthesis, Test synthesis and Placement
o
Test
pattern generation and simulation with Test Data Volume Reduction implemenation
o
RTL
to gate and initial gate to optimized placed gates formal verification
ü BlueTooth digital block design on a
130nm
o
Digital
block floorplanning and Power routing
o
Static
Power Analysis
o
Physical
Verification
Within Philips:
ü CD/DVD encoder/decoder block
implementation in a 0.18um and 0.15um(shrink)
4 layer process flow, in production and very successful:
o
Full block implementation of up to 600k Gates
using 9 memories
o
Optimization
and cost area improvement work
o
Test
strategy and clock tree implementation with embedded clock generator composed
of multiple different clock domains running up to a 135 MHz
o
Analogue
and Pad+PCB timing model generation
o
Synchronous
interface implemented and running up to 209 MHz
o
Fine
tuning of constraints and STA analysis performed abroad
o
Multiple
ECO’s and IPO’s due to system level fixes
ü Automation and GUI scripting
o
Physical
Clock tree report summary
o
Timing
Clock tree report summary
o
PKS
to Pearl constraint translator with GUI
o
Full
STA automation, including GUI, capable of generating and running application
and test modes
o
STA
timing report debugger
ü Improvement projects
o
Performed
Spice path analysis on critical nets using STA to spice conversion
o
Implemented
analogue timing model for use with STA interface analysis
o
Studied
scan chains relative theory and implementation
EDUCATION
1999-2000 DESS Microelectronics,
(equivalent
to Post Graduate Degree in Microelectronics, 5 years after A-level)
Nov
1999 Realisation
of a physical chip from masks to encapsulation and test in one week in a
University laboratory.
PERSONAL
Born
in
Regularly
play
LANGUAGES
French:
mother tongue
English: fluent
Portuguese: intermediate
Spanish:
intermediate
Russian:
beginner